1. Field of the Invention
The present invention relates to an integrated circuit device having a test circuit as well as a functional circuit on a surface of a circuit substrate such as a silicon semiconductor substrate with a thin film formation technology, and to a semiconductor wafer having a plurality of integrated circuit devices partitioned through scribing areas.
2. Description of the Prior Art
Integrated circuit devices such as ICs (Integrate Circuit) and LSIs (Large Scale Integration) are used in various types of electronic equipment. Such a integrated circuit device typically comprises a single rectangular circuit substrate, on which surface a functional circuit is formed with a thin-film formation technology for implementing various functions to be performed by the integrated circuit. As a circuit substrate, a silicon semiconductor substrate, a GaAs semiconductor substrate or the like is generally used.
When an integrated circuit device configured as described above is fabricated, typically, a silicon wafer is provided as a single large substrate and a surface thereof is sectioned into a plurality of circuit substrates through a scribing area. The plurality of circuit substrates are formed for respective integrated circuit devices to be mass-produced at a time from a single silicon wafer, while the scribing area is formed as a cutting margin for dividing the silicon wafer into respective circuit substrates.
The sectioning into circuit substrates is actually performed simultaneously with the formation of circuits with exposure utilizing a mask. The formation of functional circuits of the same pattern in a plurality of circuit substrates results in the same integrated circuit devices mass-produced from a single silicon wafer.
However, when functional circuits are formed with a thin-film formation technology such as the aforementioned exposure, defects in manufacture may occur in integrated circuit devices due to various types of manufacturing errors. Specifically, semiconductor circuits are typically formed by stacking layer films of various shapes, in which case defects may occur due to various types of errors.
Factors of such defects include variations in various dimensions, variations in misalignment at an alignment step, or the like. For example, in the case of an MIS (Metal-Insulator-Semiconductor) transistor, since a gate length of a transistor determines performance and reliability of a functional circuit, variations in the gate length in manufacturing steps causes reduced yields including performance and reliability. Additionally, if alignment accuracy is not ensured at various alignment steps, a leakage current flows or a short-circuit occurs in portions which should be electrically insulated, which may cause defects.
It is necessary to determine a completed integrated circuit device is satisfactory or not. However, since an enormous number of functional elements are integrated in a functional circuit at a high density, it is difficult to individually test the functional elements for determining whether each of them is satisfactory or not. For this reason, a measure is taken that a monitor transistor is formed simultaneously with a functional circuit at the manufacture of an integrated circuit device for testing the presence or absence of manufacturing errors by the monitor transistor.
A technology for forming a monitor transistor together with a functional circuit is disclosed, for example, in JP-A-62-229952, JP-A-63-250119, JP-A-03-262145, JP-A-05-055322, JP-A-05-172896, or the like.
Among them, JP-A-62-229952 and JP-A-63-250119 disclose that a monitor transistor is formed in a scribing area of a silicon wafer to allow the test of manufacturing errors without preventing the scale of integration of an integrated circuit device.
In integrated circuit devices disclosed in JP-A-03-262145 and JP-A-05-055322, monitor transistors are formed in respective four corners of a rectangular circuit substrate. This enables the test of manufacturing errors in substantially the whole area of a circuit substrate.
In an integrated circuit device disclosed in JP-A-05-172896, a p-channel MOS (Metal Oxide Semiconductor) transistor and an n-channel MOS transistor are formed as monitor transistors on a single circuit substrate. This enables the test of characteristics of both a p-channel MOS transistor and n-channel MOS transistor.
Presently, design rules for integrated circuit devices are increasingly detailed, and it becomes very difficult to improve various dimensional accuracy and alignment accuracy at an alignment step.
Integrated circuit devices such as CMOS (Complementary MOS) circuits after 0.15 xcexcm generation exhibit extremely reduced yields and reliability if the dimensional accuracy and alignment accuracy can not be ensured. For example, when a gate length is reduced in dimension below a defined value, or when a displacement of a gate electrode with respect to a diffusion layer formed at the previous step causes a reduction in a projecting length of the gate electrode into the diffusion layer, a leakage current above an allowable value flows between a source and drain of a transistor, rendering the transistor defective.
On the other hand, in recent years, a chip size per integrate circuit device tends to be increased due to higher performance of integrated circuit devices. Additionally, multi-image products are increased in number for the purpose of improving productivity and reducing manufacturing time. For this reason, it is necessary to make the most of an effective exposure area of an exposure system, although it is generally known that dimensional accuracy and alignment accuracy are reduced in outer regions of an exposure shot.
The causes of the reduced dimensional accuracy and alignment accuracy in outer regions of an exposure shot include distortion of a projection lens, errors in movement of a scanning stage, errors in detection or arrangement of pattern alignment, errors in detection of reticle alignment, or changes over time of movable sections or a detection system. These causes are complicatedly combined to increase manufacturing errors in outer regions of an exposure shot.
In this manner, the detailed design rule and the increased effective exposure area contribute to an increased number of defects caused by manufacturing errors at an exposure step. As described above, various errors caused by exposure are significantly found in outer regions of an exposure shot. Monitor transistors disposed in those regions for suppressing manufacturing errors lead to improvement in yields as well as improvement in reliability of integrated circuit devices.
The referenced prior art technologies enable the test of manufacturing errors without preventing the scale of integration of integrated circuit devices, the test of manufacturing errors in substantially the whole area of a circuit substrate, the test of characteristics of both a p-channel MOS transistor and n-channel MOS transistor, or the like.
However, all of the aforementioned prior art technologies can test manufacturing errors only in one direction and can not test defects in a two-dimensionally formed integrated circuit device favorably . For example, let it be assumed that an MIS transistor formed on a circuit substrate as a functional circuit has a gate electrode oriented in an x-direction and its insufficient gate length causes an abnormal current to flow between a source and drain. In this case, if a gate electrode of a monitor transistor is oriented in a y-direction, the abnormality can not be detected even with monitor transistors disposed at four corners of the circuit substrate, rendering the integrate circuit device defective.
Additionally, in an integrated circuit device in which monitor transistors having their gate electrodes projecting in the positive y-direction with respect to a diffusion layer are disposed at four corners of a circuit substrate, the monitor transistors can not detect an abnormality that occurs when a gate electrode of an MIS transistor formed as a functional circuit on the circuit substrate is displaced in a negative y-direction to cause an abnormal current to flow between a source and drain.
In this manner, since a prior art monitor transistor has a gate electrode projecting in one direction from a gap between a source region and drain region, it is impossible to detect all of manufacturing errors in various directions caused by exposure. In a typical integrated circuit device, since a functional circuit is two-dimensionally formed with a configuration corresponding to four directions of xc2x1x-directions and xc2x1y-directions, the test of manufacturing errors only in one direction as described above does not provide a reliable test of defects in a integrated circuit device.
An object of the present invention to provide an integrated circuit device capable of testing manufacturing errors in a plurality of directions.
Another object of the present invention to provide a semiconductor wafer capable of testing manufacturing errors of a integrated circuit device in a plurality of directions.
The first object of the present invention is achieved by an integrated circuit device comprising a functional circuit, and a test circuit including a plurality of MIS transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another.
In the integrated circuit device, various functions assigned to the integrated circuit can be exerted with the functional circuit. Since the plurality of MIS transistors forming the test circuit each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another, manufacturing errors in the functional circuit can be tested with the plurality of MIS transistors in a plurality of directions to favorably detect a defective integrated circuit device.
In an embodiment of the integrated circuit device according to the present invention, the test circuit includes a pair of MIS transistors, the pair of MIS transistors has the gate electrodes projecting in directions opposite to each other, and a pair of the gate electrodes is formed from opposite end portions of an electrode layer in the same axial direction. This allows the test of manufacturing errors in the functional circuit in a pair of opposite directions. At this time, since the gate electrodes of the pair of MIS transistors are formed from the end portions of a single electrode layer, the pair of MIS transistor forming the test circuit has a simple configuration.
The shape of the integrated circuit device is a predetermined polygon for example, and typically a rectangle. In this case, the test circuit may be disposed at an inner position of a vertex of the polygon. Since the disposition of the test circuit in this manner means that the test circuit is located in the outer region of the integrated circuit device, manufacturing errors in the functional circuit can be tested in substantially the whole area of the integrated circuit device.
The second object of the present invention is achieved by a semiconductor wafer comprising a plurality of integrated circuit devices each including a functional circuit, a scribing area for separating the plurality of integrated circuit devices, and a test circuit, located in the scribing area, including a plurality of MIS transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another.
The semiconductor wafer according to the present invention is cut off with the scribing area to result in a number of integrated circuit devices mass-produced at a time. The integrated circuit device thus manufactured can generate various functions with functional circuit. Since the test circuit is formed in the scribing area of the semiconductor wafer and the plurality of MIS transistors forming the test circuit each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another, manufacturing errors in the functional circuit of the integrated circuit device can be tested with the plurality of MIS transistors in a plurality of directions. The test circuit for testing the functional circuit of the integrated circuit device thus formed in the scribing area of the semiconductor wafer causes no reduction in scale of integration of the integrated circuit device due to the formation of the test circuit. Since manufacturing errors in the functional circuit can be tested with the plurality of MIS transistors in a plurality of directions, it is possible to satisfactorily detect defective integrated circuit devices mass-produced from the semiconductor wafer. The test circuit for testing the functional circuit of the integrated circuit device is formed in the scribing area of the semiconductor wafer, thereby providing a favorable scale of integration of the integrated circuit device.
The above and other objects, features, and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate examples of preferred embodiments of the present invention.